1. Field of the Invention
The present invention relates to a method for fabricating an image sensor.
2. Description of Related Art
A recent emerging technology in the field of solid state sensors involves forming image sensors using complementary metal oxide silicon (CMOS) processing. With their ability to electronically duplicate functions of the human eye, CMOS image sensors are capable of acting as highly intelligent information collectors by integrating image processing circuitry on the same chip as the sensor.
A CMOS image sensor includes a photosensitive part, receiving the light and accumulating photocharges, and a logic circuit part, transforming the photocharges into electric signals and generating data. To improve the photosensitivity of the image sensor, there have been continuing endeavors to increase the area ratio (fill factor) of the photosensitive part in the unit pixel to the total area of the image sensor. However, there are fundamental limits in such endeavors, because the logic circuit parts can not be completely eliminated and thus, the photosensitive part exists in a limited area.
One option to address this issue is to use a light-collecting technique. This technique generally employs a microlens system that is built on the upper face of the CMOS device. In this arrangement, the microlens system focuses and concentrates the light onto the photosensitive surface instead of allowing it to fall on non-photosensitive areas of the device.
FIG. 1 represents a cross-sectional view of a CMOS image sensor 100 fabricated in accordance with the related art.
As can be seen in FIG. 1, CMOS image sensor 100 comprises a field insulating layer 102 that is formed on a field area of a semiconductor substrate 101, such as the area of a single crystalline silicon substrate. Image sensor 100 also comprises a unit pixel including a photodiode 103 of a photodetector, which is formed on the active area of the semiconductor substrate 101.
Image sensor 100 further includes a multi-layer interconnect structure constructed on the upper surface of the photodiode. This multi-layer interconnect structure comprises a first interconnect 104, made of polycrystalline silicon and formed on the field insulating layer 102. As shown in FIG. 1, a first dielectric 105, providing electrical insulation between layers, is deposited and planarized on top of the first interconnect 104.
The multi-layer interconnect structure also comprises a second interconnect 106, which is made of aluminum and formed on the first dielectric layer 105. A second dielectric layer 107, which ensures electrical insulation between layers, is deposited and planarized on top of the first dielectric 105 and the second interconnect 106.
Similarly, the multi-layer structure in FIG. 1 further comprises a third interconnect 108, which is made of aluminum and formed on the second dielectric 107. As shown in FIG. 1, a third dielectric layer 109 is deposited and planarized on top of the second dielectric 107 and the third interconnect 108 in order to provide electrical insulation between layers.
Image sensor 100 also comprises a light blockage layer 110 made of aluminum and formed on the third dielectric 109. Image sensor 100 further includes a circular or rectangular opening (not shown in FIG. 1) that is provided in the central area of the light blockage layer 110 so that light can impinge on the photosensitive area 103 of device 100.
As can be seen in FIG. 1, a fourth dielectric 111 is deposited on the upper face of the third dielectric 109 and the light blockage 110. The fourth dielectric 111 acts as a protective layer against external moisture and scratches and can be composed of either a single layer of oxide or nitride or a laminated layer of oxide and nitride.
As also can be seen in FIG. 1, image sensor 100 comprises a color filter 112 of colorant material that is formed on the fourth dielectric 111. Image sensor 100 further includes an over coating material (OCM) 113 of photosensitive material, which is disposed on the color filter 112 and which regulates a focal length of the microlens 114 formed on the OCM. Image sensor 100 finally includes an oxide layer 115 disposed on the microlens 114, which consists, for example, of a low temperature oxide (LTO) SiH4 formed by Plasma Enhanced Chemical Vapor Deposition (PECVD).
In operation, the external light beam, which is incident on the microlens 114, is filtered into several light beams having different wavelengths, (corresponding to, for example, red, green or blue) while penetrating the color filter 112. The filtered light beam then propagates through the multi-layer structure of the image sensor 100 (fourth dielectric 111, third dielectric 109, second dielectric 107, and first dielectric 105) and impinges on the photodiode 103. The characteristics of the image sensor 100 are determined by the light received on the photodiode 103 and depend from the reflection, refraction and absorption coefficients of the microlens 114, OCM 113, color filter 112 and fourth, third, second and first dielectrics 111, 109, 107 and 105 respectively.
Following their manufacture, individual CMOS sensors, which are formed as a chip on a semiconductor substrate, are packaged in order to provide electrical connections to an external system and protection from deleterious environmental factors (e.g., moisture). To facilitate the use of uniformly sized packages and to reduce substrate resistance, semiconductor wafers are usually thinned prior to packaging of the individual semiconductor devices. Such thinning is referred to as “back grinding,” since it is conventionally accomplished by mechanically grinding the lower surface (i.e., back) of the semiconductor wafer.
Stress and shocks generated by backgrinding, however, may have a dramatic impact on the characteristics of the CMOS image sensor, and in particular on the microlens. This is due to the fact that during this operation the upper surface of the substrate is firmly grounded to a support, thereby exposing the microlens to scratches and potential fatal shocks. It is therefore crucial to develop new image sensor manufacturing processes wherein the performances of the CMOS sensor are not impacted during back grinding.